verilog - Difference between Behavioral, RTL and gate Level -

i'm trying understand differences between abstraction levels of verilog, description of each level says still can't on play.

for case, paste verilog codes , think them:

1. the following code in behavioral level.

   always  @ (a or b or sel)   begin     y = 0;     if (sel == 0) begin       y = a;     end else begin     y = b;   end end 

2. this (just example) in gate level

   module test(clk,  ready, next, q);   input clk, enable, next;   output q;    \**seqgen** reg_1 (.clear(1'b0), .next_state(next), .clocked_on(clk), .q(q), .synch_enable(enable) );  endmodule 

3. i don't know if code in rtl or gate level ( expect keyword make rtl , not gate level )

   module dff_from_nand();   wire q,q_bar;   reg d,clk;    nand u1 (x,d,clk) ;   nand u2 (y,x,clk) ;   nand u3 (q,q_bar,x);   nand u4 (q_bar,q,y);    // testbench of above code   initial begin     $monitor("clk = %b d = %b q = %b q_bar = %b",clk, d, q, q_bar);     clk = 0;     d = 0;     #3  d = 1;     #3  d = 0;     #3  $finish;   end        #2  clk = ~clk;  endmodule 

i know initial begin , end not synthesizeable , used testing. have 2 questions

1. third (and second) code rtl or gate-leve? rtl code example? found rtl code example rtl? me looks behavioral level.

2. what means verilog netlist? same gate level or have context base definition?

i'm confused because in websites don't know if they're saying 'this verilog code using logic gates' or 'this verilog code in gate-level'

i happy if wants explain more details topic :)

rtl : register-transfer-level, abstraction hardware functionality written always blocks , assign statements synthesizable (can translated gate level). pure rtl not instantiate sub-modules. rtl contain sub-modules guide synthesizer. structural rtl (ofter still called rtl) module contains other rtl modules. example: fsm (finite-state-machine)

always @* begin   next_state = state;   if (count>0) next_count = count - 1;   case (state)   idle :     if(do_start) begin       next_state = start;       next_count = 2;     end   start :     if (do_wait) begin       next_count = count;     end     else if (count==0) begin       next_state = run;       next_count = count_from_input;     end   run :     if (do_stop) begin       next_state = idle;     end     if (do_wait) begin       next_count = count;     end     else if (count==0) begin       next_state = idle;     end   endcase end @(posedge clk, negedge rst_n) begin   if (!rst_n) begin     count <= 0;     state <= idle;   end   else begin     count <= next_count;     state <= next_state;   end end 

behavioral : mimics desired functionality of hardware not synthesizable. there no strict rules long code generates desired behavior. guideline keep simple , readable. behavioral used represent analog block, place holder code (rtl/gates not ready), , testbench code. example: clock generator, delay cells.

always begin   if (!clk_en && clk==1'b1) begin     wait (clk_en);   end   #5 clk = ~clk; end 

the key difference between rtl , behavioral ability synthesize. behavioral if see # delay, wait statements, while loops, force/release statements, or hierarchical reference. technically there rare excusable exceptions, out of scope if question.

gate-level (aka structural) : logic described gates , modules only. no always blocks or assign statements. representative of real gates in hardware.

verilog netlist collection of verilog modules used in design. can 1 or many files. can mix of of rtl, behavioral , structural. structural, large designs.