Verilog: "... is not a constant" -


i have 3 wires created this:

wire [11:0] magnitude; wire [3:0] bitsend; wire [3:0] leadingbits;

all of them assigned expression using combinational logic. following code works fine:

assign leadingbits[3] = magnitude[bitsend + 3]; assign leadingbits[2] = magnitude[bitsend + 2]; assign leadingbits[1] = magnitude[bitsend + 1]; assign leadingbits[0] = magnitude[bitsend + 0];

however, following (seemingly equivalent) code gives error bitsend not constant:

assign leadingbits[3:0] = magnitude[bitsend + 3:bitsend];

can not use shorthand assignment? why error raised in second case not first?

in verilog can't use variable (i.e. bitsend) end of range. can use +:/-: operator solve issue:

assign leadingbits = magnitude[bitsend+3 -: 4];

in first case calculate single index (it's not range). that's why compiler not complaining it.


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