compiler construction - Data Forwarding to a subsequent lw instruction -


say have 2 mips instructions 1 after other, so.

i1: add $12, $15, $14

i2: lw $15, 100($12)

after instruction 1 has reached stage in mips pipeline i2's lw able read $12? how many times lw, therefore, end stalling (how many 'bubbles' need)? i'm not sure how far lw can progress without waiting $12 updated.

i'm guessing i1 need reach , complete mem first, not sure if wb needs happen before can load 100($12).

my understanding mips pipeline goes if-id-ex-mem-wb.


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